High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

H. Takato, K. Sunouchi, N. Okabe, Akihiro Nitayama, K. Hieda, F. Horiguchi, F. Masuoka

研究成果: Conference article査読

97 被引用数 (Scopus)

抄録

A novel transistor with compact structure has been developed for MOS devices. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. For example, the occupied area of a CMOS inverter can be shrunk to 50% of that using planar transistors. The other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability. These features are due to the unique structure, which results in greater gate controllability and in electric field relaxation at the drain edge.

本文言語English
ページ(範囲)222-225
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 1988 12 1
イベントTechnical Digest - International Electron Devices Meeting 1988 - San Francisco, CA, USA
継続期間: 1988 12 111988 12 14

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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