High-performance ASIC implementations of the 128-bit block cipher CLEFIA

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

研究成果: Conference contribution

11 被引用数 (Scopus)

抄録

In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/IEC 18033-3 standard block ciphers (AES, Camellia, SEED, CAST-128, MISTY1, and TDEA). We designed five types of hardware architectures for CLEFIA, combining two loop structures and three F-functions. These designs were synthesized with a 90-nm CMOS standard cell library, and size and speed performances were evaluated. The highest hardware efficiency (defined as throughput/gates) obtained was 400.96 Kbps/gates, which is 1.5 times higher than previously achieved efficiencies.

本文言語English
ホスト出版物のタイトル2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
ページ2925-2928
ページ数4
DOI
出版ステータスPublished - 2008 9 19
イベント2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
継続期間: 2008 5 182008 5 21

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(印刷版)0271-4310

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
国/地域United States
CitySeattle, WA
Period08/5/1808/5/21

ASJC Scopus subject areas

  • 電子工学および電気工学

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