Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMTs (E-HEMTs) are described for the first time. Most important for the fabrication of E-HEMTs is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step-recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. Etching selectivities for both steps are sufficient not to degrade the uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-inch wafer. A cutoff frequency of 208 GHz and a maximum frequency of oscillation of 460 GHz are obtained for the 0.1-μm-gate E-HEMTs. This technology for E-HEMTs are promising candidates for ultra-highspeed applications.
|ジャーナル||Conference Proceedings - International Conference on Indium Phosphide and Related Materials|
|出版ステータス||Published - 1998 12月 1|
|イベント||Proceedings of the 1998 International Conference on Indium Phosphide and Related Materials - Tsukuba, Jpn|
継続期間: 1998 5月 11 → 1998 5月 15
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