Hardware implementation of an inverse function delayed neural network using stochastic logic

Hongge Li, Yoshihiro Hayakawa, Shigeo Sato, Koji Nakajima

研究成果: Article査読

2 被引用数 (Scopus)

抄録

In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.

本文言語English
ページ(範囲)2572-2578
ページ数7
ジャーナルIEICE Transactions on Information and Systems
E89-D
9
DOI
出版ステータスPublished - 2006 1 1

ASJC Scopus subject areas

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • コンピュータ ビジョンおよびパターン認識
  • 電子工学および電気工学
  • 人工知能

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