Gate-tuned negative differential resistance observed at room temperature in an array of gold nanoparticles

Tran Thi Thu Huong, Kazuhiko Matsumoto, Masataka Moriya, Hiroshi Shimada, Yasuo Kimura, Ayumi Hirano-Iwata, Yoshinao Mizugaki

研究成果: Article査読

6 被引用数 (Scopus)

抄録

We fabricated a single-electron (SE) device using gold nanoparticles (Au NPs). Drain, source, and gate electrodes on a SiO2/Si substrate were formed using electron beam lithography (EBL) and thermal evaporation of Au. Subsequently, solutions of 3-nm-diameter and 5-nm-diameter Au NPs were dropped on the device to make current paths through Au NPs among the electrodes. Measurements of the device exhibited negative differential resistance (NDR) in the current–voltage characteristics between the drain and source electrodes at room temperature (298 K). The NDR behavior was tuned by applying a gate voltage.

本文言語English
論文番号268
ジャーナルApplied Physics A: Materials Science and Processing
123
4
DOI
出版ステータスPublished - 2017 4 1
外部発表はい

ASJC Scopus subject areas

  • 化学 (全般)
  • 材料科学(全般)

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