Gate length scaling of high-k vertical MOSFET toward 20nm CMOS technology and beyond

Takeshi Sasaki, Tetsuo Endoh

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

This paper presents the gate length scaling of the Vertical MOSFET (VMOS) with high-k dielectrics for beyond 20nm CMOS technology in comparison with Double Gate MOSFET (DG) at the same Drain Induced Barrier Lowering (DIBL). The VMOS can significantly suppresses DIBL within 11mV/V caused by fringing electric field through thicker designed high-k dielectrics (EOT=1.0nm). Moreover, the VMOS can be designed by shorter gate length from 5.4 to 19nm as using higher gate dielectric constant from k=10 to k=60.

本文言語English
ホスト出版物のタイトル2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013
出版社IEEE Computer Society
ISBN(印刷版)9781479913602
DOI
出版ステータスPublished - 2013 1 1
イベント2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013 - Monterey, CA, United States
継続期間: 2013 10 72013 10 10

出版物シリーズ

名前2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013

Other

Other2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013
国/地域United States
CityMonterey, CA
Period13/10/713/10/10

ASJC Scopus subject areas

  • 電子工学および電気工学

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