This paper presents a new design method for multiplierless 2-D state-space digital filters (SSDFs). In order to eliminate multipliers in the hardware implementation, the resulting multiplierless 2-D SSDFs are designed under the constraint that all coefficients are represented by the sum of two powers-of-two terms. Thus they are attractive for low cost implementation and high-speed operation, since the signal in the filters can be processed by fewer shifting operations and additions instead of multiplications. Because of having very low roundoff noise, they can also perform highly accurate 2-D digital filtering. Here a combinatorial optimization procedure called genetic algorithm has been used to determine the coefficients. The effectiveness of the proposed method is demonstrated with a design example.
|出版ステータス||Published - 1996 12月 1|
|イベント||Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea|
継続期間: 1996 11月 18 → 1996 11月 21
|Other||Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems|
|City||Seoul, South Korea|
|Period||96/11/18 → 96/11/21|
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