A novel source-coupled logic (SCL) style using multiple-valued signals, called multiple-valued source-coupled logic (MVSCL), which operates with an input voltage swing of about 0.3V, is proposed for high-speed and low-power VLSI systems. A multiple-valued comparator, which is a key component, is realized by using differential-pair circuits (DPCs), so that its power dissipation can be greatly reduced while maintaining high-speed switching. Moreover, the current-source control allows steady current flow to cut off when the circuit is not active, thereby saving power dissipation. A 54×54-bit signed-digit multiplier based on MVSCL is designed in a 0.35-μm CMOS technology, and its performance is superior to both corresponding binary static CMOS and multiple-valued current-mode (MVCM) implementation.
|ジャーナル||Proceedings of The International Symposium on Multiple-Valued Logic|
|出版ステータス||Published - 2002 1月 1|
|イベント||32nd IEEE International Symposium on Multiple-Valued Logic - Boston, MA, United States|
継続期間: 2002 5月 15 → 2002 5月 18
ASJC Scopus subject areas
- コンピュータ サイエンス（全般）
- 数学 (全般)