Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs

T. Amazawa, E. Yamamoto, K. Sakuma, Y. Ito, K. Kamoshida, K. Ikeda, K. Saito, H. Ishii, S. Kato, S. Yagi, K. Hiraoka, T. Ueki, T. Takeda, Y. Arita

研究成果: Conference article査読

2 被引用数 (Scopus)

抄録

The chemical mechanical polishing (CMP) of selective aluminum (Al) CVD via plugs is examined for the first time and a fully planarized four-level interconnection system with all stacked via plugs is demonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plug has proved to be one of the best via plug structures because of its low via resistance and extremely high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4 μ m, equal pitch, four-level interconnection.

本文言語English
ページ(範囲)473-476
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 1995 12 1
イベントProceedings of the 1995 International Electron Devices Meeting, IEDM'95 - Washington, DC, USA
継続期間: 1995 12 101995 12 13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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