Fully-parallel VLSI implementation of vector quantization processor using neuron-MOS technology

Akira Nakada, Masahiro Konda, Tatsuo Morimoto, Takemi Yonezawa, Tadashi Shibata, Tadahiro Ohmi

    研究成果: Article査読

    7 被引用数 (Scopus)

    抄録

    An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-μm double-polysilicon CMOS technology with the chip size of 7.2 mm × 7.2 mm, and the basic operation of the circuits has been demonstrated.

    本文言語English
    ページ(範囲)1730-1737
    ページ数8
    ジャーナルIEICE Transactions on Electronics
    E82-C
    9
    出版ステータスPublished - 1999 1月 1

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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