An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-μm double-polysilicon CMOS technology with the chip size of 7.2 mm × 7.2 mm, and the basic operation of the circuits has been demonstrated.
|ジャーナル||IEICE Transactions on Electronics|
|出版ステータス||Published - 1999 1月 1|
ASJC Scopus subject areas