FPGA implementation of binarized perceptron learning hardware using CMOS invertible logic

研究成果: Conference contribution

抄録

This paper introduces FPGA implementation of learning hardware for a neural network. The proposed learning hardware is designed using CMOS invertible logic that realizes probabilistic bidirectional (forward and backward) operations with basic CMOS logic gates. The backward operation based on CMOS invertible logic makes hardware-based learning possible because the loss function is not required. For a simple case study, the proposed learning hardware trains using simplified a MNIST data set for a 25-input binarized perceptron. Our FPGA implementation on Digilent Genesys 2 achieves around 100 x faster operating speed than that using a traditional learning algorithm on software while maintaining the same recognition accuracy of 99%.

本文言語English
ホスト出版物のタイトル2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
出版社Institute of Electrical and Electronics Engineers Inc.
ページ115-116
ページ数2
ISBN(電子版)9781728109961
DOI
出版ステータスPublished - 2019 11
イベント26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 - Genoa, Italy
継続期間: 2019 11 272019 11 29

出版物シリーズ

名前2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

Conference

Conference26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
国/地域Italy
CityGenoa
Period19/11/2719/11/29

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 制御と最適化
  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ

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