FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture

Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama, Yasuhiro Kobayashi

研究成果: Conference contribution

16 被引用数 (Scopus)

抄録

This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and- pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor(Pentium4@2GHz), and is enough to generate a 3-D depth image at the video rate of 33MHz.

本文言語English
ホスト出版物のタイトル2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
ページ1219-1222
ページ数4
DOI
出版ステータスPublished - 2005 12 1
イベント2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States
継続期間: 2005 8 72005 8 10

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
2005
ISSN(印刷版)1548-3746

Other

Other2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
CountryUnited States
CityCincinnati, OH
Period05/8/705/8/10

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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