FPGA-Based Scalable and Power-Efficient Fluid Simulation using Floating-Point DSP Blocks

Kentaro Sano, Satoru Yamamoto

研究成果: Article査読

18 被引用数 (Scopus)

抄録

High-performance and low-power computation is required for large-scale fluid dynamics simulation. Due to the inefficient architecture and structure of CPUs and GPUs, they now have a difficulty in improving power efficiency for the target application. Although FPGAs become promising alternatives for power-efficient and high-performance computation due to their new architecture having floating-point (FP) DSP blocks, their relatively narrow memory bandwidth requires an appropriate way to fully exploit the advantage. This paper presents an architecture and design for scalable fluid simulation based on data-flow computing with a state-of-the-art FPGA. To exploit available hardware resources including FP DSPs, we introduce spatial and temporal parallelism to further scale the performance by adding more stream processing elements (SPEs) in an array. Performance modeling and prototype implementation allow us to explore the design space for both the existing Altera Arria10 and the upcoming Intel Stratix10 FPGAs. We demonstrate that Arria10 10AX115 FPGA achieves 519 GFlops at 9.67 GFlops/W only with a stream bandwidth of 9.0 GB/s, which is 97.9 percent of the peak performance of 18 implemented SPEs. We also estimate that Stratix10 FPGA can scale up to 6844 GFlops by combining spatial and temporal parallelism adequately.

本文言語English
論文番号7893769
ページ(範囲)2823-2837
ページ数15
ジャーナルIEEE Transactions on Parallel and Distributed Systems
28
10
DOI
出版ステータスPublished - 2017 10 1

ASJC Scopus subject areas

  • 信号処理
  • ハードウェアとアーキテクチャ
  • 計算理論と計算数学

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