Formal design of multiple-valued arithmetic algorithms over galois fields and its application to cryptographic processor

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

This paper presents a formal description of multiple-valued arithmetic algorithms over Galois Fields (GFs). Our graph-based method can be applied to any multiple-valued arithmetic circuit over GF(2 m). The proposed circuit description is formally verified by formula manipulation based on polynomial reduction using Groebner basis. In this paper, we first present the graph representation and its extension. We also present an application of the proposed method to cryptographic processor consisting of GF(2 m) arithmetic circuits. The target architecture considered here is a round-per-cycle loop architecture commonly used in the design of cryptographic processors. The proposed approach successfully describes the 128-bit data path and verifies it within 4 minutes.

本文言語English
ホスト出版物のタイトルProceedings - IEEE 42nd International Symposium on Multiple-Valued Logic, ISMVL 2012
ページ110-115
ページ数6
DOI
出版ステータスPublished - 2012
イベント42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012 - Victoria, BC, Canada
継続期間: 2012 5 142012 5 16

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012
CountryCanada
CityVictoria, BC
Period12/5/1412/5/16

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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