The high frequency characteristics of DTMOS is described here for the first time. Our DTMOS has a small parasitic resistance due to an optimized Co salicide technology and a small parasitic capacitance due to a reduction in the overlapped region between the gate and drain, which is achieved by gate poly-Si oxidation before LDD implantation. We obtained an Ft of 78 GHz and an Fmax of 37 GHz for a 0.1-μm-Leff DTMOS even at a supply voltage of 0.7 V. We also noted an Fmax enhancement of 1.5 times compared to that of a conventional SOI MOSFET, which is attributed to a high transconductance and a large output resistance.
|ジャーナル||Technical Digest - International Electron Devices Meeting, IEDM|
|出版ステータス||Published - 1997 12月 1|
|イベント||1997 International Electron Devices Meeting - Washington, DC, USA|
継続期間: 1997 12月 7 → 1997 12月 10
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