TY - JOUR
T1 - Fmax enhancement of dynamic threshold-voltage MOSFET (DTMOS) under ultra-low supply voltage
AU - Tanaka, Tetsu
AU - Momiyama, Youichi
AU - Sugii, Toshihiro
PY - 1997/12/1
Y1 - 1997/12/1
N2 - The high frequency characteristics of DTMOS is described here for the first time. Our DTMOS has a small parasitic resistance due to an optimized Co salicide technology and a small parasitic capacitance due to a reduction in the overlapped region between the gate and drain, which is achieved by gate poly-Si oxidation before LDD implantation. We obtained an Ft of 78 GHz and an Fmax of 37 GHz for a 0.1-μm-Leff DTMOS even at a supply voltage of 0.7 V. We also noted an Fmax enhancement of 1.5 times compared to that of a conventional SOI MOSFET, which is attributed to a high transconductance and a large output resistance.
AB - The high frequency characteristics of DTMOS is described here for the first time. Our DTMOS has a small parasitic resistance due to an optimized Co salicide technology and a small parasitic capacitance due to a reduction in the overlapped region between the gate and drain, which is achieved by gate poly-Si oxidation before LDD implantation. We obtained an Ft of 78 GHz and an Fmax of 37 GHz for a 0.1-μm-Leff DTMOS even at a supply voltage of 0.7 V. We also noted an Fmax enhancement of 1.5 times compared to that of a conventional SOI MOSFET, which is attributed to a high transconductance and a large output resistance.
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M3 - Conference article
AN - SCOPUS:84886448027
SP - 423
EP - 426
JO - Technical Digest - International Electron Devices Meeting
JF - Technical Digest - International Electron Devices Meeting
SN - 0163-1918
T2 - 1997 International Electron Devices Meeting
Y2 - 7 December 1997 through 10 December 1997
ER -