Flexible processor based on full-adder/D-flip-flop merged module

S. Sakaidani, N. Miyamoto, T. Ohmi

研究成果: Conference contribution

抄録

Flexible processor based on full-adder/D-flip-flop merged module (FDMM) has been designed and fabricated. The developed FDMM has unique ability to perform both logic and flip-flop functions with a small transistor count by merging the common part of both circuits. We have also developed a context memory block to reconfigure the hardware dynamically. The flexible processor may fill a gap between hardware performance and software programmability to jump into novel computing such as software/hardware synthesis; "software accelerator".

本文言語English
ホスト出版物のタイトルProceedings of the ASP-DAC 2001
ホスト出版物のサブタイトルAsia and South Pacific Design Automation Conference 2001
出版社Institute of Electrical and Electronics Engineers Inc.
ページ35-36
ページ数2
ISBN(電子版)0780366336
DOI
出版ステータスPublished - 2001 1月 1
イベントAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
継続期間: 2001 1月 302001 2月 2

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2001-January

Other

OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
国/地域Japan
CityYokohama
Period01/1/3001/2/2

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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