A technological platform is established for scalable flexible hybrid electronics based on a novel fan-out wafer-level packaging (FOWLP) methodology. Small dielets are embedded in flexible substrates we call FlexTrate. These dielets can be interconnected through high-density wirings formed in wafer-level processing. We demonstrate homogeneous integration of 625 (25 by 25) 1-mm2 Si dielets and heterogeneous integration of GaAs and Si dielets with various thicknesses in a biocompatible polydimethylsiloxane (PDMS). In this paper, 8-μm-pitch die-to-die interconnections are successfully implemented over a stress buffer layer formed on the PDMS. In addition, coplanarity between the PDMS and embedded dielets, die shift concerned in typical die-first FOWLP, and the bendability of the resulting FlexTrate are characterized.
|ジャーナル||IEEE Transactions on Components, Packaging and Manufacturing Technology|
|出版ステータス||Published - 2018 10|
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering