Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS

M. Kadoshima, Y. Sugita, K. Shiraishi, H. Watanabe, A. Ohta, S. Miyazaki, K. Nakajima, T. Chikyow, K. Yamada, T. Aminaka, E. Kurosawa, T. Matsuki, T. Aoyama, Y. Nara, Y. Ohji

研究成果: Conference article査読

19 被引用数 (Scopus)

抄録

We propose here cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is "positively" utilized to reduce threshold voltages for the first time. After systematic investigation on the relation between oxygen vacancies in Hf-based high-k film and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In our proposed method, source of oxygen interstitials (Al) is contained in metal gate material for p-FET, and consequently the flamand voltage is properly modulated by "opposite" Fermi-level pinning due to the oxygen interstitials incorporated into the underlying high-k film after high temperature annealing. It is also noteworthy that this method is simple and cost-effective because the initial high-k films are identical for n- and p-FET but they are automatically converted into dual high-k after the annealing process.

本文言語English
論文番号4339729
ページ(範囲)66-67
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
DOI
出版ステータスPublished - 2007
イベント2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
継続期間: 2007 6 122007 6 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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