We propose here cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is "positively" utilized to reduce threshold voltages for the first time. After systematic investigation on the relation between oxygen vacancies in Hf-based high-k film and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In our proposed method, source of oxygen interstitials (Al) is contained in metal gate material for p-FET, and consequently the flamand voltage is properly modulated by "opposite" Fermi-level pinning due to the oxygen interstitials incorporated into the underlying high-k film after high temperature annealing. It is also noteworthy that this method is simple and cost-effective because the initial high-k films are identical for n- and p-FET but they are automatically converted into dual high-k after the annealing process.
|ジャーナル||Digest of Technical Papers - Symposium on VLSI Technology|
|出版ステータス||Published - 2007|
|イベント||2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan|
継続期間: 2007 6 12 → 2007 6 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering