抄録
A novel retention analysis method for ferroelectric random access memory (FeRAM) has been developed, in which read signal voltages from memory cells are measured. It employs on-chip sample/hold circuits, an off-chip A/D converter, and memory LSI testing equipment. FeRAM chip reliability is estimated on the basis of FeRAM read signal voltages after retention periods of 1 day and longer. When used as a tool to estimate long-term data retention in FeRAM chips, and when used to analyze fluctuations in FeRAM cell characteristics, this method can be of significant help in improving the reliability of FeRAM chips.
| 本文言語 | English |
|---|---|
| ページ | 37-41 |
| ページ数 | 5 |
| 出版ステータス | Published - 2001 1月 1 |
| 外部発表 | はい |
| イベント | ICMTS 2001. 2001 International Conference on Microelectronic Test Structures - Kobe, Japan 継続期間: 2001 3月 19 → 2001 3月 22 |
Other
| Other | ICMTS 2001. 2001 International Conference on Microelectronic Test Structures |
|---|---|
| 国/地域 | Japan |
| City | Kobe |
| Period | 01/3/19 → 01/3/22 |
ASJC Scopus subject areas
- 電子工学および電気工学