Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates

Miroslav Knežević, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Kocabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki

研究成果: Article

24 引用 (Scopus)

抜粋

The first contribution of our paper is that we propose a platform, a design strategy, and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. Using a SASEBO-GII field-programmable gate array (FPGA) board as a common platform, combined with well defined hardware and software interfaces, we compare all 256-bit version candidates with respect to area, throughput, latency, power, and energy consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specification for the SHA-3 module on our testing platform. The second contribution is that we provide both FPGA and 90-nm CMOS application-specific integrated circuit (ASIC) synthesis results and thereby are able to compare the results. Our third contribution is that we release the source code of all the candidates and by using a common, fixed, publicly available platform, our claimed results become reproducible and open for a public verification.

元の言語English
記事番号5756688
ページ(範囲)827-840
ページ数14
ジャーナルIEEE Transactions on Very Large Scale Integration (VLSI) Systems
20
発行部数5
DOI
出版物ステータスPublished - 2012 5

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Knežević, M., Kobayashi, K., Ikegami, J., Matsuo, S., Satoh, A., Kocabas, Ü., Fan, J., Katashita, T., Sugawara, T., Sakiyama, K., Verbauwhede, I., Ohta, K., Homma, N., & Aoki, T. (2012). Fair and consistent hardware evaluation of fourteen round two SHA-3 candidates. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(5), 827-840. [5756688]. https://doi.org/10.1109/TVLSI.2011.2128353