Fabrication technologies for doubIe-SiO2-barrier metal-oxide-semiconductor transistor with a poly-Si dot

Tsuyoshi Hatano, Yuhei Ito, Ann Nakajima, Shin Yokoyama

研究成果: Article査読

1 被引用数 (Scopus)

抄録

A double-tunnel-barrier (1.7-nm-thick SiO2) metal-oxide-semiconductor (MOS) transistor with a poly-Si dot was proposed as a single-electron transistor (SET). The simulation results indicated that room-temperature operation of the SET is possible when the poly-Si dot size is in the order of ∼10nm. Technologies for the fabrication of the MOS transistor were developed. We have evalulated plasma-induced damage at the sidewall of the Si trench in which a poly-Si dot is embedded. It was found that a sacrificial oxidation of 20 nm is necessary to remove the plasma-induced damage. In order to assure complete electrical isolation of the source and the drain by the trench, simulation of the impurity (arsenic, phosphorous and boron) profiles for the MOS transistor with a trench (200 nm length × 200 nm depth) were carried out. Test MOS transistors with a poly-Si dot (200 nm length × 200 nm height × 50-100 nm width) were fabricated. However, the device showed an abnormally large current which may be ascribed to the residual poly-Si in the trench outside of the dot region.

本文言語English
ページ(範囲)2017-2020
ページ数4
ジャーナルJapanese Journal of Applied Physics, Part 2: Letters
40
3 B
DOI
出版ステータスPublished - 2001
外部発表はい

ASJC Scopus subject areas

  • 工学(全般)
  • 物理学および天文学(全般)

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