抄録

A nonvolatile FPGA (NVFPGA) test chip, where 3000 6-input lookup table (LUT) circuits are embedded, is fabricated under 90nm CMOS/75nm perpendicular magnetic tunnel junction (p-MTJ) technologies. The use of a p-MTJ device makes data-backup-limitation free, which essentially eliminates damage control to nonvolatile storage devices. The use of a p-MTJ device also enables the extension towards dynamically reconfigurable logic paradigm. Since hardware components are shared among all the p-MTJ devices by the use of logic-in-memory structure, the effective area of the 6-input LUT circuit is reduced by 56% compared to that of an SRAM-based one. Moreover, block-level power gating, in which all the idle function blocks are optimally turned off in accordance with the operation mode, can minimize static power consumption of each tile. As a result, the total average power of the proposed NVFPGA is reduced by 81% in comparison with that of an SRAM-based FPGA under typical benchmark-circuit realizations.

本文言語English
ホスト出版物のタイトル2015 Symposium on VLSI Circuits, VLSI Circuits 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ページC172-C173
ISBN(電子版)9784863485020
DOI
出版ステータスPublished - 2015 8 31
イベント29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan
継続期間: 2015 6 172015 6 19

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers
2015-August

Other

Other29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
国/地域Japan
CityKyoto
Period15/6/1715/6/19

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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