Excellent weight-updating-linearity synapse memory cell for self-learning neuron MOS neural networks

Hideo Kosaka, Tadashi Shibata, Hiroshi Ishii, Tadahiro Ohm

研究成果: Conference contribution

5 引用 (Scopus)

抜粋

A new synapse cell circuit employing a floating-gate memory has been developed which is characterized by an excellent weight-updating linearity. Such a feature has been realized for the first time by employing a simple self-feedback regime in each cell circuit. The new cell is composed of only seven transistors and inherits the all advanced features of our old six-transistor cell [1], such as the standby--power free and dual polarity characteristics, thus making it fully compatible to the hardware learning architecture of the Neuron MOS neural network. The basic characteristics of the cell are demonstrated using test circuits fabricated by a double-polysilicon CMOS process.

元の言語English
ホスト出版物のタイトルTechnical Digest - International Electron Devices Meeting
編集者 Anon
出版者Publ by IEEE
ページ623-626
ページ数4
ISBN(印刷物)0780314506
出版物ステータスPublished - 1993 12 1
イベントProceedings of the 1993 IEEE International Electron Devices Meeting - Washington, DC, USA
継続期間: 1993 12 51993 12 8

出版物シリーズ

名前Technical Digest - International Electron Devices Meeting
ISSN(印刷物)0163-1918

Other

OtherProceedings of the 1993 IEEE International Electron Devices Meeting
Washington, DC, USA
期間93/12/593/12/8

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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  • これを引用

    Kosaka, H., Shibata, T., Ishii, H., & Ohm, T. (1993). Excellent weight-updating-linearity synapse memory cell for self-learning neuron MOS neural networks. : Anon (版), Technical Digest - International Electron Devices Meeting (pp. 623-626). (Technical Digest - International Electron Devices Meeting). Publ by IEEE.