Evolutionary graph generation with terminal-colour constraint for heterogeneous circuit synthesis

M. Natsui, T. Aoki, T. Higuchi

研究成果: Article査読

5 被引用数 (Scopus)

抄録

A novel graph-based evolutionary optimisation technique that can be used to synthesise heterogeneous circuits consisting of various different components is proposed. The key idea is to introduce 'circuit graphs with coloured terminals' for modelling heterogeneous architectures. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.

本文言語English
ページ(範囲)808-810
ページ数3
ジャーナルElectronics Letters
37
13
DOI
出版ステータスPublished - 2001 6 21

ASJC Scopus subject areas

  • 電子工学および電気工学

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