Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

研究成果: Article

1 引用 (Scopus)

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As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips.

元の言語English
記事番号04EC07
ジャーナルJapanese journal of applied physics
55
発行部数4
DOI
出版物ステータスPublished - 2016 4 1

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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