Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture

研究成果: Conference contribution

抄録

The capacity and the energy consumption of the last-level cache (LLC) must be improved toward future microprocessors. This paper proposes an STT-RAM-based hybrid cache architecture (HCA) and its replacement policy, named the Fast Region First Used (FRFU) policy. The proposed HCA is composed of two types of STT-RAM devices with different characteristics to mitigate the disadvantages of non-volatile STT-RAM devices. The FRFU policy provides the better handling of the data blocks for the proposed HCA than the LRU policy. The evaluation results show that the proposed HCA and its policy can successfully reduce the energy consumption by 55% and improve the performance by 1% on average compared with a conventional SRAM LLC.

本文言語English
ホスト出版物のタイトルIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781728163475
DOI
出版ステータスPublished - 2020 4
イベント23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Kokubunji, Japan
継続期間: 2020 4 152020 4 17

出版物シリーズ

名前IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings

Conference

Conference23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020
国/地域Japan
CityKokubunji
Period20/4/1520/4/17

ASJC Scopus subject areas

  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • ハードウェアとアーキテクチャ
  • ソフトウェア
  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理

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