Electroless Cu seed on Ru and Co liners in high aspect ratio TSV

F. Inoue, H. Philipsen, M. H. Van Der Veen, S. Van Huylenbroeck, S. Armini, H. Struyf, T. Tanaka

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

High aspect ratio through-silicon vias (3 μm diameter by 50 μm depth) have been filled by standard Cu plating process on electroless deposited (ELD) Cu seed layers on conformal liners of Ru or Co. The in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm. This is much lower than would have been needed in a conventional scheme with a PVD-Cu seed (of ∼ 1500 nm) and, with that, reduces the Cu CMP time. This work shows the feasibility of Cu electroless as deposition technique in a TSV metallization process.

本文言語English
ホスト出版物のタイトル2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference, IITC/AMC 2014
出版社IEEE Computer Society
ページ207-210
ページ数4
ISBN(印刷版)9781479950164
DOI
出版ステータスPublished - 2014 1 1
イベント2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference, IITC/AMC 2014 - San Jose, CA, United States
継続期間: 2014 5 202014 5 23

出版物シリーズ

名前2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference, IITC/AMC 2014

Other

Other2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference, IITC/AMC 2014
CountryUnited States
CitySan Jose, CA
Period14/5/2014/5/23

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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