Electrical properties of lanthanum-scandate gate dielectric directly deposited on Ge

The electrical performance of both Ge MOSCAP and MOSFET with LaScO _x high-k gate dielectric directly deposited on Ge (100) without utilizing any interfacial passivation layer has been investigated. This study also reports about the control of V_fb/V_th through ScO concentration. Accordingly, a relatively larger hysteresis and higher density of interface states with ScO concentration having lower or higher than 50% along with increasing annealing temperatures were observed in general as a result of deterioration caused by the formation of GeO_x at the interface in conjunction with more pronounce intermixing or Ge out-diffusion into LaScO _x. Nevertheless, an ultrathin Si passivation layer is found to be advantageous to inhibit Ge incorporation into high-k bulk in the form of GeO_x, thereby diminishing the resultant oxide charge trapping as well as improves the thermal stabilities of the entire LaScO_x/Ge MOS structures. Besides, reasonably good electrical properties of Ge p-MOSFETs with LaScO_x gate dielectric have been demonstrated.