A new current mirror with a biasing current source is proposed for high-performance arithmetic VLSI systems. The delay for the current mirror is inversely proportional to the input current. The use of a biasing current source makes the input current of the current mirror increased, which results in smaller switching delay. As a typical example of the proposed dual-rail multiple-valued current mode (MVCM) circuit, a radix-2 signed-digit full adder is designed by using a 0.35-μm CMOS technology. Its performance is superior to that of corresponding MVCM circuits without biasing current sources.
|ジャーナル||Proceedings of The International Symposium on Multiple-Valued Logic|
|出版ステータス||Published - 2001 1 1|
|イベント||31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001) - Warsaw, Poland|
継続期間: 2001 5 22 → 2001 5 24
ASJC Scopus subject areas
- コンピュータ サイエンス（全般）
- 数学 (全般)