Dual-rail multiple-valued current-mode VLSI with biasing current sources

T. Ike, T. Hanyu, M. Kameyama

研究成果: Conference article査読

8 被引用数 (Scopus)

抄録

A new current mirror with a biasing current source is proposed for high-performance arithmetic VLSI systems. The delay for the current mirror is inversely proportional to the input current. The use of a biasing current source makes the input current of the current mirror increased, which results in smaller switching delay. As a typical example of the proposed dual-rail multiple-valued current mode (MVCM) circuit, a radix-2 signed-digit full adder is designed by using a 0.35-μm CMOS technology. Its performance is superior to that of corresponding MVCM circuits without biasing current sources.

本文言語English
ページ(範囲)21-26
ページ数6
ジャーナルProceedings of The International Symposium on Multiple-Valued Logic
出版ステータスPublished - 2001 1 1
イベント31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001) - Warsaw, Poland
継続期間: 2001 5 222001 5 24

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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