Deteriorated device characteristics in 3D-LSI caused by distorted silicon lattice

Murugesan Mariappan, Yasuhiko Imai, Shigeru Kimura, Takafumi Fukushima, Ji Choel Bea, Hisashi Kino, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

研究成果: Article査読

5 被引用数 (Scopus)

抄録

Silicon-lattice distortion in the 50-μ-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ∼1000 MPa of tensile stress and ∼200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

本文言語English
論文番号6701183
ページ(範囲)540-547
ページ数8
ジャーナルIEEE Transactions on Electron Devices
61
2
DOI
出版ステータスPublished - 2014 2

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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