We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This method-ology advantages from using gm/ID as a primary design parameter to con-sider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the g m/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combina-tion of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to ex-plore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of g m/IDS as well as circuit param-eters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125 MS/s pipeline A/D converter imple-mented in a 0.18μm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweak-ing of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.
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