Design of tamper-resistant registers for multiple-valued cryptographic processors

Yuichi Baba, Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.

本文言語English
ホスト出版物のタイトルISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic
ページ67-72
ページ数6
DOI
出版ステータスPublished - 2010 8 12
イベント40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010 - Barcelona, Spain
継続期間: 2010 5 262010 5 28

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010
国/地域Spain
CityBarcelona
Period10/5/2610/5/28

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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