Design of robust-fault-tolerant arithmetic circuits and their application

Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi

研究成果: Conference article査読

2 被引用数 (Scopus)

抄録

Robust-fault-tolerant arithmetic circuits for a highly safe digital system are proposed. Two kinds of robust-fault-tolerant arithmetic circuits based on distributed coding are designed. One is a robust-fault-tolerant adder, and the other is a robust-fault-tolerant multiplier. It is shown in an experiment of robot control that the safety of the proposed arithmetic circuits is superior to that of the ordinary binary arithmetic circuits.

本文言語English
ページ(範囲)2748-2751
ページ数4
ジャーナルProceedings - IEEE International Symposium on Circuits and Systems
4
出版ステータスPublished - 1990 12 1
イベント1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
継続期間: 1990 5 11990 5 3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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