Design of micropower CMOS quaternary memory circuits

Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi

研究成果: Article査読

抄録

In a previous paper the authors proposed a pass transistor network composed of PMOS and NMOS transistors with different threshold voltages, which were realized by a multilevel ion‐implant technique. As a result, any quaternary logic system could be implemented. In the quaternary CMOS make‐break operator circuit, which is the basic cell of the network, the steady‐state current is essentially zero and therefore micro‐power quaternary combinational circuits can be implemented. In this paper, a micropower quaternary D‐latch circuit is designed using quaternary CMOS make‐break operator circuits. Then using the D‐latch circuit as a unit, a quaternary master‐slave flip‐flop and an up‐down T‐flip‐flop circuit are designed. Computer simulation for these circuits with SPICE‐2 confirmed their correct operation with low power dissipation. The power dissipation during the transient increases in proportion to the operating frequency. Also, a quaternary maximal‐length sequence generator is designed as an application.

本文言語English
ページ(範囲)61-69
ページ数9
ジャーナルSystems and Computers in Japan
18
11
DOI
出版ステータスPublished - 1987

ASJC Scopus subject areas

  • 理論的コンピュータサイエンス
  • 情報システム
  • ハードウェアとアーキテクチャ
  • 計算理論と計算数学

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