Design of lsi‐oriented digital signal processing system Based on Pulse‐Train Residue Arithmetic Circuits

Nobuhiro Tomabechi, Michitaka Kameyama, Tatsuo Higuchi

研究成果: Article査読

抄録

This paper describes a design method of high‐speed digital signal processing systems suitable for LSI fabrication. It utilizes the pulse‐train residue arithmetic circuit as a basic building block. This circuit lends itself to parallel and pipeline operations suitable f o r high‐speed digital signal processing, and permits modular‐design of the systems. A new master‐slice LSI on which the pulse‐train residue arithmetic circuits are arranged regularly, is presented. A method of minimizing the chip‐area for NMOS fabrication of the master‐slice is discussed. The layout of the pulse train residue arithmetic circuits on the LSI chip, and several parameters of the master‐slice such as the number of channels are discussed. Some demonstrative examples are presented to show the application of the master‐slice in the design of digital filter. The design method using master‐slices is relatively simple; it minimizes the chip‐count and improves the processing speed.

本文言語English
ページ(範囲)76-84
ページ数9
ジャーナルSystems and Computers in Japan
17
6
DOI
出版ステータスPublished - 1986

ASJC Scopus subject areas

  • 理論的コンピュータサイエンス
  • 情報システム
  • ハードウェアとアーキテクチャ
  • 計算理論と計算数学

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