Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.

Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod mi multiplication can be simply performed by a shift operation. In mod mi addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10-μm CMOS technology.

本文言語English
ホスト出版物のタイトルProceedings of The International Symposium on Multiple-Valued Logic
出版社Publ by IEEE
ページ6-13
ページ数8
ISBN(印刷版)0818608595
出版ステータスPublished - 1988 12 1

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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