Design of a processing element based on quaternary differential logic for a multi-core SIMD processor

Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto

研究成果: Conference contribution

17 引用 (Scopus)

抜粋

A high-speed, low-power and compact processing element (PE) using quaternary differential logic is proposed for a multi-core single-instruction multiple-data (SIMD) processor. A two-bit addition which is the critical path of the ALU is attributed to a one-digit quaternary addition that is directly performed by using multiple-valued currentmode (MVCM) differential logic circuitry. A one-digit quaternary flip-flop is also simply implemented by using the MVCM differential logic circuitry. The efficiency of the proposed quaternary PE is demonstrated using 0.18μm CMOS HSPICE simulation in comparison with a corresponding CMOS implementation.

元の言語English
ホスト出版物のタイトル37th International Symposium on Multiple-Valued Logic, ISMVL 2007
DOI
出版物ステータスPublished - 2007 9 3
イベント37th International Symposium on Multiple-Valued Logic, ISMVL 2007 - Oslo, Norway
継続期間: 2007 5 132007 5 16

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷物)0195-623X

Other

Other37th International Symposium on Multiple-Valued Logic, ISMVL 2007
Norway
Oslo
期間07/5/1307/5/16

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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  • これを引用

    Shirahama, H., Mochizuki, A., Hanyu, T., Nakajima, M., & Arimoto, K. (2007). Design of a processing element based on quaternary differential logic for a multi-core SIMD processor. : 37th International Symposium on Multiple-Valued Logic, ISMVL 2007 [4215966] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2007.14