Design of a multiple-valued rule-programmable matching VLSI chip for real-time rule-based systems

Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

A multivalued VLSI processor design for fully parallel pattern matching is presented. It can be applied to real-time rule-based systems with large knowledge bases which are programmable. One-digit pattern matching based on direct multivalued encoding of each attribute can be described by only a programmable delta literal. Moreover, the literal circuit can be easily implemented using two floating-gate MOS devices whose threshold voltages are controllable. The inference time of an eight-valued matching processor with 256 rules and conflict resolution circuits is estimated at about 360 ns, and the chip area is reduced to about 10% of that of the equivalent binary implementation.

本文言語English
ホスト出版物のタイトルProceedings of The International Symposium on Multiple-Valued Logic
出版社Publ by IEEE
ページ274-281
ページ数8
ISBN(印刷版)0818626801
出版ステータスPublished - 1992 5月 1
外部発表はい
イベントProceedings of the 22nd International Symposium on Multiple-Valued Logic - Sendai, Jpn
継続期間: 1992 5月 271992 5月 29

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

OtherProceedings of the 22nd International Symposium on Multiple-Valued Logic
CitySendai, Jpn
Period92/5/2792/5/29

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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