Design of a microprocessor datapath using four-valued differential-pair circuits

Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

New four-valued logic and static storage components using differential-pair circuits (DPCs) are proposed for a high-performance microprocessor datapath. The DPC-based circuit makes a signal-voltage swing small yet the current-driving capability large, and generates complementary outputs. Both a four-valued comparator and a binary static latch can be merged into a simple DPC-based circuit structure, which achieves low-power dissipation and small chip area while maintaining high-speed switching. As a typical application, a 32-bit microprocessor datapath with five pipelining stages is implemented using the proposed circuit technique in 0.18μm CMOS, and its advantages are demonstrated in comparison with a corresponding CMOS implementation.

本文言語English
ホスト出版物のタイトル36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
ページ数1
DOI
出版ステータスPublished - 2006 11 21
イベント36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 - Singapore, Singapore
継続期間: 2006 5 172006 5 20

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
国/地域Singapore
CitySingapore
Period06/5/1706/5/20

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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