Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme

Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

A new packet data transfer scheme (PDTS) is introduced to reduce a configuration/control memory (CCM) size of a multiple-valued dynamic reconfigurable VLSI based on a logic-in-memory architecture. In the PDTS, the CCM size for memory access is proportional not to the number of distributed memory modules in the reconfigurable VLSI, but to the number of read operations in all the memories. Thus, remarkable reduction of the CCM size can be achieved in comparison with the conventional control scheme. Moreover, the PDTS contributes to fine-grain ON/OFF control of the current sources in Differential-Pair Circuits (DPCs) utilizing flag information which indicates whether the data is valid or invalid.

本文言語English
ホスト出版物のタイトルProceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014
出版社IEEE Computer Society
ページ214-219
ページ数6
ISBN(印刷版)9781479935345
DOI
出版ステータスPublished - 2014
イベント44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014 - Bremen, Germany
継続期間: 2014 5月 192014 5月 21

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

Other

Other44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014
国/地域Germany
CityBremen
Period14/5/1914/5/21

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 数学 (全般)

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