Design and implementation of high-speed signal processing system for 2-D state-space digital filters using distributed arithmetic

Masayuki Kawamata, Tomoo Yamakage

研究成果: Conference article査読

抄録

A high-speed signal processing system for 2-D state-space digital filters is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5-kb ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512 × 512. Thus, the proposed system can process television images in real time.

本文言語English
ページ(範囲)735-738
ページ数4
ジャーナルProceedings - IEEE International Symposium on Circuits and Systems
1
出版ステータスPublished - 1990 12 1
イベント1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
継続期間: 1990 5 11990 5 3

ASJC Scopus subject areas

  • 電子工学および電気工学

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