TY - JOUR
T1 - Design and implementation of high-speed signal processing system for 2-D state-space digital filters using distributed arithmetic
AU - Kawamata, Masayuki
AU - Yamakage, Tomoo
PY - 1990/12/1
Y1 - 1990/12/1
N2 - A high-speed signal processing system for 2-D state-space digital filters is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5-kb ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512 × 512. Thus, the proposed system can process television images in real time.
AB - A high-speed signal processing system for 2-D state-space digital filters is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5-kb ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512 × 512. Thus, the proposed system can process television images in real time.
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M3 - Conference article
AN - SCOPUS:0025671648
SN - 0271-4310
VL - 1
SP - 735
EP - 738
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4)
Y2 - 1 May 1990 through 3 May 1990
ER -