TY - JOUR
T1 - Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation
AU - Abe, Hiroki
AU - Arai, Hiroki
AU - Kawamata, Masayuki
PY - 2005/12/1
Y1 - 2005/12/1
N2 - In this paper, we design and implement an improved hardware-based evolutionary digital filter (EDF) version 2. The EDF is an adaptive digital filter which is controlled by adaptive algorithm based on evolutionary computation. The hardwarebased EDF version 1 consists of two submodules, that is, a filtering and fitness calculation (FFC) module and a reproduction and selection (RS) module. The FFC module has high computational ability to calculate the output and the fitness value since its submodules run in parallel. However, hardware size of the FFC module is large, and many machine cycles are needed. Thus, in the hardware-based EDF version 2, we combine the two modules to reduce its hardware size and machine cycles. A synthesis result on the FPGA shows the clock frequency is 65.5MHz and the maximum sampling rate of the hardware-based EDF version 2 is 4,948.1Hz. Moreover, the hardware-based EDF version 2 is 15.7 times faster than the hardware-based EDF version 1.
AB - In this paper, we design and implement an improved hardware-based evolutionary digital filter (EDF) version 2. The EDF is an adaptive digital filter which is controlled by adaptive algorithm based on evolutionary computation. The hardwarebased EDF version 1 consists of two submodules, that is, a filtering and fitness calculation (FFC) module and a reproduction and selection (RS) module. The FFC module has high computational ability to calculate the output and the fitness value since its submodules run in parallel. However, hardware size of the FFC module is large, and many machine cycles are needed. Thus, in the hardware-based EDF version 2, we combine the two modules to reduce its hardware size and machine cycles. A synthesis result on the FPGA shows the clock frequency is 65.5MHz and the maximum sampling rate of the hardware-based EDF version 2 is 4,948.1Hz. Moreover, the hardware-based EDF version 2 is 15.7 times faster than the hardware-based EDF version 1.
UR - http://www.scopus.com/inward/record.url?scp=67649118556&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67649118556&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1464641
DO - 10.1109/ISCAS.2005.1464641
M3 - Conference article
AN - SCOPUS:67649118556
SP - 528
EP - 531
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
M1 - 1464641
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -