Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA

Daisuke Suzuki, Takahiro Hanyu

研究成果: Conference contribution

抄録

A nonvolatile FPGA, where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, a synthesizable nonvolatile FPGA is proposed, where the circuit-configuration information is described in a hardware description language and is pushed through a standard ASIC tool flow with nonvolatile logic circuit IPs such as nonvolatile flip-flops. The use of the ASIC tool flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical design example under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, the performance of the proposed nonvolatile FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.

本文言語English
ホスト出版物のタイトルProceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020
出版社IEEE Computer Society
ページ194-199
ページ数6
ISBN(電子版)9781728154060
DOI
出版ステータスPublished - 2020 11
イベント50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020 - Miyazaki, Japan
継続期間: 2020 11 92020 11 11

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
2020-November
ISSN(印刷版)0195-623X

Conference

Conference50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020
CountryJapan
CityMiyazaki
Period20/11/920/11/11

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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