Design and evaluation of a 67% area-less 64-bit parallel reconfigurable 6-input nonvolatile logic element using domain-wall motion devices

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu

研究成果: Article査読

7 被引用数 (Scopus)

抄録

A 6-input nonvolatile logic element (NV-LE) using domain-wall motion (DWM) devices is presented for low-power and real-time reconfigurable logic LSI applications. Because the write current path of a DWM device is separated from its read current path and the resistance value of the write current path is quite small, multiple DWM devices can be reprogrammed in parallel, thus affording real-time logic-function reconfiguration within a few nanoseconds. Moreover, by merging a circuit component between combinational and sequential logic functions, transistor counts can be minimized. As a result, 2-ns 64-bit-parallel circuit reconfiguration is realized by the proposed 6-input NV-LE with 67% lesser area than a conventional CMOS-based alternative, with a simulation program with integrated circuit emphasis (SPICE) simulation under a 90 nm CMOS/MTJ technologies.

本文言語English
論文番号04EM03
ジャーナルJapanese journal of applied physics
53
4 SPEC. ISSUE
DOI
出版ステータスPublished - 2014 1 1

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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