Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip

Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Toshinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masakazu Muraguchi, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

To realize a high-density spin-transfer-torque magnetic random access memory (STT-MRAM) device comparable with a current dynamic random access memory (DRAM) device, it is a key to develop a new technology for memory cell size reduction. We have already reported a chemical-mechanical-polishing(CMP)-based preparation technology for magnetic tunnel junctions (MTJs) above the via holes that can drastically reduce memory cell area. In this paper, we first introduce the MTJ preparation technology to the mega-bit class STT-MRAM test chip, and demonstrate the improvement of memory-cell operation yield.

本文言語English
ホスト出版物のタイトル2016 IEEE 8th International Memory Workshop, IMW 2016
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781467388313
DOI
出版ステータスPublished - 2016 6 15
イベント8th IEEE International Memory Workshop, IMW 2016 - Paris, France
継続期間: 2016 5 152016 5 18

出版物シリーズ

名前2016 IEEE 8th International Memory Workshop, IMW 2016

Other

Other8th IEEE International Memory Workshop, IMW 2016
国/地域France
CityParis
Period16/5/1516/5/18

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ

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