@inproceedings{d231adfbdb864c3ba639dfa7a7a03b17,
title = "Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip",
abstract = "To realize a high-density spin-transfer-torque magnetic random access memory (STT-MRAM) device comparable with a current dynamic random access memory (DRAM) device, it is a key to develop a new technology for memory cell size reduction. We have already reported a chemical-mechanical-polishing(CMP)-based preparation technology for magnetic tunnel junctions (MTJs) above the via holes that can drastically reduce memory cell area. In this paper, we first introduce the MTJ preparation technology to the mega-bit class STT-MRAM test chip, and demonstrate the improvement of memory-cell operation yield.",
keywords = "CMP, MTJ, STT-MRAM, bit yield, cell size",
author = "Hiroki Koike and Sadahiko Miura and Hiroaki Honjo and Toshinari Watanabe and Hideo Sato and Soshi Sato and Takashi Nasuno and Yasuo Noguchi and Mitsuo Yasuhira and Takaho Tanigawa and Masakazu Muraguchi and Masaaki Niwa and Kenchi Ito and Shoji Ikeda and Hideo Ohno and Tetsuo Endoh",
note = "Funding Information: This work was supported in part by CIES's Industrial Affiliation on the STT MRAM program, ImPACT Program of CSTI, and ACCEL Program under JST. The test chip design was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc. and Mentor Graphics, Inc. Publisher Copyright: {\textcopyright} 2016 IEEE.; 8th IEEE International Memory Workshop, IMW 2016 ; Conference date: 15-05-2016 Through 18-05-2016",
year = "2016",
month = jun,
day = "15",
doi = "10.1109/IMW.2016.7495264",
language = "English",
series = "2016 IEEE 8th International Memory Workshop, IMW 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 IEEE 8th International Memory Workshop, IMW 2016",
}