Demonstration of split-gate type trigate flash memory with highly suppressed over-erase

Takahiro Kamei, Yongxun Liu, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'Uchi, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Tetsuro Hayashida, Kunihiro Sakamoto, Atsushi Ogura, Meishoku Masahara

研究成果: Article査読

12 被引用数 (Scopus)

抄録

The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (V t) variations before and after nor-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (L CG) of 176 nm show much smaller V t distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BV DS) is higher than 3.1 V even the L CG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled nor-type flash memory with highly suppressed over-erase.

本文言語English
論文番号6145732
ページ(範囲)345-347
ページ数3
ジャーナルIEEE Electron Device Letters
33
3
DOI
出版ステータスPublished - 2012 3月
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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