A new blind oversampling clock and data recovery (BO-CDR) algorithm is proposed. It has high tolerance to low-frequency jitter (14.8 unit intervals at 10 kHz, measured at 640 Mbps) and is suitable for systems where the receiver clock has high drift with respect to the transmission. The algorithm is capable of recovering data over a wide tracking range or when the precise oversampling rate (β) is not known a priori, for any real-valued oversampling rate, β ≥ 3, making this BO-CDR algorithm the first to not require integer-valued β. To demonstrate the utility of the algorithm, two implementations are designed and evaluated. The first is used in a low-power, low-data rate sensor node IC with a low-performance single phase clock source. The second is a high-speed receiver with a multiple phase clock source implemented on FPGA. The CDR core consists of just 47 logic cells and 19 registers and has an estimated power consumption of 0.70 mW at 640 Mbps. The properties of this CDR algorithm make it appropriate for a wide range of applications in serial communication.