Delay window blind oversampling clock and data recovery algorithm with wide tracking range

Travis Bartley, Shuji Tanaka, Yutaka Nonomura, Takahiro Nakayama, Masanori Muroyama

研究成果: Conference contribution

17 被引用数 (Scopus)

抄録

A new blind oversampling clock and data recovery (BO-CDR) algorithm is proposed. It has high tolerance to low-frequency jitter (14.8 unit intervals at 10 kHz, measured at 640 Mbps) and is suitable for systems where the receiver clock has high drift with respect to the transmission. The algorithm is capable of recovering data over a wide tracking range or when the precise oversampling rate (β) is not known a priori, for any real-valued oversampling rate, β ≥ 3, making this BO-CDR algorithm the first to not require integer-valued β. To demonstrate the utility of the algorithm, two implementations are designed and evaluated. The first is used in a low-power, low-data rate sensor node IC with a low-performance single phase clock source. The second is a high-speed receiver with a multiple phase clock source implemented on FPGA. The CDR core consists of just 47 logic cells and 19 registers and has an estimated power consumption of 0.70 mW at 640 Mbps. The properties of this CDR algorithm make it appropriate for a wide range of applications in serial communication.

本文言語English
ホスト出版物のタイトル2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ページ1598-1601
ページ数4
ISBN(電子版)9781479983919
DOI
出版ステータスPublished - 2015 7月 27
イベントIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
継続期間: 2015 5月 242015 5月 27

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
2015-July
ISSN(印刷版)0271-4310

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
国/地域Portugal
CityLisbon
Period15/5/2415/5/27

ASJC Scopus subject areas

  • 電子工学および電気工学

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