Degradation of memory retention characteristics in DRAM chip by Si thinning for 3-D integration

Kangwook Lee, Seiya Tanikawa, Mariappine Murugesan, Hideki Naganuma, Haro Shimamoto, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

研究成果: Article査読

18 被引用数 (Scopus)

抄録

The Young's modulus (E) of Si substrate begin to noticeably decrease below 50-μm thickness. The Young's modulus in 30-μm thick Si substrate decreased by 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si atom is highly distorted. Large distortion of the lattice structure induces the Young's modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-μm thickness is bonded to a Si interposer and thinned down to 50/40/30/20-μm thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreasing of the chip thickness, especially dramatically degraded below 50-μm thickness. The retention time of DRAM cell in the 20-μm thick chip is shortened by ∼40% compared to the 50-μm thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects carrier recombination rates, consequently a shortening retention time of DRAM cell.

本文言語English
論文番号6531648
ページ(範囲)1038-1040
ページ数3
ジャーナルIEEE Electron Device Letters
34
8
DOI
出版ステータスPublished - 2013 6 20

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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