We have developed a new A/D converter architecture by applying the concept of Clocked-Neuron-MOS circuitry. It features no dc power dissipation at any component in the A/D converter. In this architecture a comparator employs dynamic latch and the reference voltage is generated by a capacitive voltage divider configuration. As a results, all components in the A/D converter have become purely dynamic in their operation, resulting in a dramatic reduction in the power dissipation. These techniques have been combined with a flash and a two-step flash mechanism, and extremely-low-power A/D converters have been developed. Test circuits were fabricated using standard double-polysilicon CMOS process with 3-μm rules. The basic performance has been confirmed by the measurement of test circuits as well as by HSPICE simulation.
|ジャーナル||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版ステータス||Published - 1996 1月 1|
|イベント||Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA|
継続期間: 1996 5月 12 → 1996 5月 15
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